Electronic apparatus having two circuit boards electrically connected to each other

ABSTRACT

An electronic apparatus includes a housing, a first circuit board including a first engaging portion configured to fix the first circuit board to the housing, and a first terminal, and a second circuit board including a second engaging portion configured to fix the second circuit board to the housing, and a second terminal electrically connected to the first terminal.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2014-259506, filed Dec. 22, 2014, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to an electronicapparatus, in particular an electronic apparatus having two circuitboards electrically connected to each other.

BACKGROUND

An electronic apparatus includes a semiconductor device having acontroller and a semiconductor memory.

DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a system configuration of a semiconductor deviceaccording to a first embodiment.

FIG. 2 is a perspective view of a host device containing thesemiconductor device therein.

FIG. 3 is a partial cross-sectional view of a tablet type portablecomputer.

FIG. 4 illustrates the semiconductor device according to the firstembodiment.

FIG. 5 is a cross-sectional view of a NAND memory and a controller inthe semiconductor device.

FIG. 6 is a block diagram of a system configuration of the controller.

FIG. 7 is a perspective view of a connector unit in the semiconductordevice according to one example.

FIG. 8 is a perspective view of a connector unit in the semiconductordevice according to another example.

FIG. 9 is a top cross-sectional view of the connector unit.

FIG. 10 illustrates a main board of the host device.

FIG. 11 is a perspective view of a connector unit.

FIG. 12 illustrates a semiconductor device according to a secondembodiment.

FIG. 13 is a side cross-sectional view of the semiconductor device and amain board according to the second embodiment.

FIG. 14 is a side view of a semiconductor device and a main boardaccording to a third embodiment.

FIG. 15 is a cross-sectional view illustrating an example of a connectorunit, an interface unit, and a cover, according to the third embodiment.

FIG. 16 is a cross-sectional view illustrating another example of theconnector unit, the interface unit, and the cover, according to thethird embodiment.

FIG. 17 is a perspective view of a connector unit, an interface unitaccording to a fourth embodiment.

FIG. 18 is a partial cross-sectional view of a tablet type portablecomputer according to a fifth embodiment.

FIG. 19 illustrates a main board according to a sixth embodiment.

FIG. 20 illustrates a semiconductor device and the main board accordingto the sixth embodiment.

DETAILED DESCRIPTION

One embodiment provides a thin electronic apparatus.

In general, according to an embodiment, an electronic apparatus includesa housing, a first circuit board including a first engaging portionconfigured to fix the first circuit board to the housing, and a firstterminal, and a second circuit board including a second engaging portionconfigured to fix the second circuit board to the housing, and a secondterminal electrically connected to the first terminal.

Hereinafter, embodiments will be described with reference to thedrawings.

In the disclosure, a plurality of expressions is used for some elements.The expressions are merely examples and may be expressed using differentexpressions. In addition, elements for which a plurality of expressionsis not used may also be expressed using different expressions.

In addition, the drawings are schematic, and a relationship between athickness and a planar dimension, a ratio of the thicknesses of eachlayer, or the like may be different from actual ones. In addition, asection in which a relationship or a ratio between dimensions isdifferent from each other in the drawings may be included.

First Embodiment

FIG. 1 illustrates a system configuration of a semiconductor device 1according to a first embodiment. The semiconductor device 1 is anexample a “semiconductor module” and a “semiconductor memory device.”The semiconductor device 1 according to the present embodiment is, forexample, a solid state drive (SSD), but is not limited thereto.

As illustrated in FIG. 1, the semiconductor device 1 according to thepresent embodiment is connected to a portable computer, which is anexample of an electronic apparatus, or to a host device 201(hereinafter, referred to as a host) such as a CPU core, via a memoryconnection interface such as an interface according to the standard,such as serial advanced technology attachment (SATA) or peripheralcomponent interconnect express (PCIe), and functions as an externalmemory of the host device 201. In addition, an interface 2 may be oneaccording to another standard.

The semiconductor device 1 receives an electric power from the hostdevice 201 via an interface. A CPU of a personal computer, a CPU of animaging device, such as a still camera or a video camera, or the likemay be used as the host device 201. In addition, the semiconductordevice 1 may perform data communication with a debug device via acommunication interface such as an RS232C interface (RS232C I/F). Inaddition, the semiconductor device 1 may be used as a storage device ofan electronic apparatus, such as a notebook type portable computer, atablet terminal, or a detachable notebook personal computer (PC).

FIG. 2 is a perspective view of the semiconductor device 1 disposed in adetachable notebook PC in which a display device side thereof isdetachable from an input device side thereof. In addition, FIG. 3 is across-sectional view of a display device side of the detachable notebookPC illustrated in FIG. 2, that is, a tablet type portable computer 201.In addition, in the detachable notebook PC, the tablet type portablecomputer 201 and an input device 218 are connected to each other througha connection unit 219. As illustrated in FIG. 2, the semiconductordevice 1 is disposed in the tablet type portable computer 201 of thedetachable notebook PC. For this reason, even if the input device sideand the display device side in the detachable notebook PC are separatedfrom each other, only the display device side may function as the tablettype portable computer 201. In addition, the tablet type portablecomputer 201 is an example of an electronic apparatus, and, for example,has a size that a user may use the tablet type portable computer 201 byholding it in his or her hand. In this case, the tablet type portablecomputer 201 functions as a host device of the semiconductor device 1.

The tablet type portable computer 201 includes a housing 202, a displaymodule 203, the semiconductor device 1, and a main board 205. Thehousing 202 includes a protection plate 206, a base 207, and a frame208. The protection plate 206 is a square plate made of glass orplastic, and configures a surface of the housing 202. The base 207 ismade of a metal, such as an aluminum alloy or a magnesium alloy, andconfigures the bottom of the housing 202.

The frame 208 is provided between the protection plate 206 and the base207. The frame 208 is made of metal, such as an aluminum alloy or amagnesium alloy, and has a mounting section 210 and a bumper section 211which are configured as one piece. The mounting section 210 is disposedbetween the protection plate 206 and the base 207. According to thepresent embodiment, the mounting section 210 defines a first mountingspace 212 between the mounting section 210 and the protection plate 206,and defines a second mounting space 213 between the mounting section 210and the base 207.

The bumper section 211 is formed in an outer circumference portion ofthe mounting section 210 and integrally with the mounting section 210,and continuously surrounds the first mounting space 212 and the mountingspace 213 in a circumferential direction. Furthermore, the bumpersection 211 extends in a thickness direction of the housing 202 so as tobe spanned between the outer circumference portion of the protectionplate 206 and the outer circumference portion of the base 207, andconfigures the outer circumference surface of the housing 202.

The display module 203 is mounted in the first mounting space 212 of thehousing 202. The display module 203 is covered with the protection plate206, and a touch panel 214, which has a handwriting input function, isdisposed between the protection plate 206 and the display module 203.The touch panel 214 adheres to the rear surface of the protection plate206.

In addition, as illustrated in FIG. 3, a plurality of first fixingsections 230 and a plurality of second fixing sections 231 are providedin the second mounting space in the housing 202. The first fixingsections 230 and the second fixing sections 231 are, for example,protrusions having screw holes, the main board 205 is fixed to theplurality of first fixing sections 230 by screws, and the semiconductordevice 1 is fixed to the plurality of second fixing sections 231 byscrews.

In addition, by aligning the heights of the protrusion sections of thefirst fixing sections 230 and the second fixing sections 231, asubstrate 11 of the semiconductor device 1 and a substrate 215 of themain board 205 are positioned on the substantially same plane.

The semiconductor device 1 is accommodated in the second mounting space213 of the housing 202 together with the main board 205. Thesemiconductor device 1 includes the substrate 11, a NAND memory 12, acontroller 13, and an electronic component such as a DRAM 14.

The substrate 11 is, for example, a printed wiring plate, and includes afirst surface 11 a (mounting surface) on which patterned conductors (notillustrated) are formed. Circuit components are disposed on the mountingsurface 11 a of the substrate 11 and are soldered to the conductorpatterns.

The main board 205 includes the substrate 215 and a plurality of circuitcomponents 216 such as semiconductor packages, and is fixed to the firstfixing section 230 of the housing 202 by screws that pass through thescrew holes 217.

The substrate 215 includes a first surface (mounting surface) 215 a onwhich a plurality of patterned conductors (not illustrated) is formed.The circuit components 216 are disposed on the mounting surface 215 a ofthe substrate 215 and are soldered to conductor patterns.

The semiconductor device 1 according to the present embodiment is asingle side mounting device in which circuit components such as the NANDmemory 12 are disposed only on the mounting surface 11 a. Thus, circuitcomponents that protrude from an external surface are not disposed on asecond surface 11 b that is opposite to the first surface 11 a. For thisreason, as illustrated in FIG. 3, the semiconductor device 1 may bedisposed in the tablet type portable computer 201 that is required tohave a thin shape.

FIG. 4 is a specific example of the semiconductor device 1. In FIG. 4,(a) is a plan view, (b) is a bottom surface view, and (c) is a sidesurface view of the semiconductor device 1. The semiconductor device 1includes the substrate 11, the NAND type flash memory (hereinafter,referred to as a NAND memory) 12, which is used as a nonvolatilesemiconductor memory element, the controller 13, the dynamic randomaccess memory (DRAM) 14, which is a volatile semiconductor memoryelement that may perform a faster storing operation than the NAND memory12, an oscillator 15 (OSC), an electrically erasable and programmableROM (EEPROM) 16, a power supply circuit 17, a temperature sensor 18, andelectronic components 19, such as a resistor and a capacitor.

In addition, the NAND memory 12 and the controller 13 according to thepresent embodiment are disposed as a semiconductor package. For example,a semiconductor package of the NAND memory 12 is a module of a system inpackage (SiP) type, and a plurality of semiconductor chips is sealed inone package. The controller 13 controls an operation of the NAND memory12.

The substrate 11 is a circuit substrate of a substantially rectangularshape and formed of a material such as glass epoxy resin, and definesthe outer dimension of the semiconductor device 1. The substrate 11includes a first surface 11 a and a second surface 11 b opposite to thefirst surface 11 a. In the present disclosure, a surface other than thefirst surface 11 a and the second surface 11 b among the surfaces thatconfigure the substrate 11 is defined as a “side surface.” The firstsurface 11 a is a component disposing surface on which the NAND memory12, the controller 13, the DRAM 14, the oscillator 15, the EEPROM 16,the power supply component 17, the temperature sensor 18, anotherelectronic component 19, such as a resistor and a capacitor, and thelike are disposed.

The substrate 11 according to the present embodiment is, for example, asingle surface mounting substrate, and all components that configure thesemiconductor device 1 are disposed on the first surface 11 a.Meanwhile, the second surface 11 b is a non-component mounting surfaceon which components are not disposed. By doing this, as described above,the semiconductor device 1 according to the present embodiment may bethinner, compared to a case in which substrate-mounted components thatprotrude from the surface are disposed on both surfaces of the substrate11.

Here, a single-surface mounting is employed, but another component orfunction may be mounted on the second surface 11 b of the substrate 11according to the present embodiment. For example, in order to easilyperform performance verification of a product, a pad for test may beprovided on the second surface. In this case, restriction for a highdensity design for providing a pad in a narrow region of the firstsurface 11 a, adjustment of a position of other components on the firstsurface 11 a, or the like is not required, and thus the degree of designfreedom of pad mounting is improved. Then, a pad electrode for test maybe provided on the second surface 11 b that is opposite to the firstsurface 11 a, whereby it is possible to shorten a wiring length forrouting, and to avoid electrical loss.

The substrate 11 has a substantially rectangular shape as describedabove, and includes a first edge 11 c that is positioned along a lateraldirection and a second edge 11 d that is positioned on a side oppositeto the first edge 11 c. The first edge 11 c includes a connector section21 (substrate interface section, terminal section, connection section).The connector section 21 includes a plurality of concave curve sections21 a (metal terminals) that is used as, for example, connectionterminals. The connector section 21 is electrically connected to thehost device 201. The connector section 21 transmits and receives signals(control signal and data signal) to and from the host device 201.

The connector section 21 according to the present embodiment is aninterface according to the standard of, for example, PCI Express (PCIe).That is, a high speed signal (high speed differential signal) accordingto the standard of the PCIe is transferred between the connector section21 and the host device 201. The connector section 21 may be oneaccording to, for example, other standards. The semiconductor device 1receives an electric power from the host device 201 via the connectorsection 21.

The power supply circuit 17 is, for example, a DC-DC converter, andgenerates a predetermined voltage necessary for the semiconductorpackage 12 or the like using electric power received from the hostdevice 201. In addition, it is preferable that the power supply circuit17 is provided in the vicinity of the connector section 21, in order toreduce loss of the electric power from the host device 201.

The controller 13 controls an operation of the NAND memory 12. That is,the controller 13 controls writing, reading, and erasing of data on theNAND memory 12.

The DRAM 14 is an example of a volatile memory, and is used for storageof management information of the semiconductor memory 32, cache of data,or the like.

The oscillator 15 supplies the controller 13 with an operation signalwith a predetermined frequency. The EEPROM 16 stores a control programor the like as fixed information. The temperature sensor 18 detectstemperature of the semiconductor device 1 and notifies the controller 13of the detected temperature.

FIG. 5 illustrates a cross section that discloses a semiconductorpackage, which is used as the NAND memory 12, and a semiconductorpackage, which is used as the controller 13, according to the presentembodiment. The controller 13 includes a package substrate 41, acontroller chip 42, a bonding wire 43, a sealing section (mold material)44, and a plurality of solder balls 45. The NAND memory 12 includes apackage substrate 31, a plurality of semiconductor memories 32, abonding wire 33, a sealing section (mold material) 34, and a pluralityof solder balls 35.

The substrate 11 is, for example, a wiring substrate with multiplelayers as described above, includes a power supply layer (notillustrated), a ground layer, and internal wires, and electricallyconnects the controller chip 42 to the plurality of semiconductormemories 32 via the bonding wires 33 and 43, the plurality of solderballs 35 and 45, and the like.

As illustrated in FIG. 5, the plurality of solder balls 35 and 45 isprovided on the package substrates 31 and 41. For example, the pluralityof solder balls 35 and 45 is arranged in a lattice pattern on a secondsurface 31 b of the package substrate 31. It is not necessary for theplurality of solder balls 35 to be fully arranged on the whole of thesecond surface 31 b of the package substrate 31, and the plurality ofsolder balls 35 may be partially arranged.

In addition, fixing of the controller chip 32 to the package substrate31, fixing of the semiconductor memory 42 to the package substrate 41,and fixing between the plurality of the semiconductor memories 42 areperformed by mount films 38 and 48.

In addition, as illustrated in FIG. 4, the controller 13 according tothe present embodiment has a substantially rectangular shape, andincludes a first edge 13 a in a lateral direction, a second edge 13 bopposite to the first edge 13 a, a third edge 13 c in a longitudinaldirection, and a fourth edge 13 d opposite to the third edge 13 c. Thesecond edge 13 b is positioned on the NAND memory 12 that is mounted onthe substrate 11 and adjacent to the controller 13, and the first edge13 a is positioned on the connector section 21 included in the substrate11.

In addition, the solder balls 45 described above include solder balls 45a that are arranged on a side of the first edge 13 a of the controller13, and solder balls 45 b that are arranged on a side of the second edge13 b. In addition, the solder balls 35 includes solder balls 35 a thatare positioned on a side of the controller 13 and solder balls 35 b thatare positioned on a side opposite to the solder balls 35 a.

FIG. 6 illustrates an example of a system configuration of thecontroller 13. As illustrated in FIG. 6, the controller 13 includes abuffer 131, a central processing unit (CPU) 132, a host interfacesection 133, and a memory interface section 134.

The buffer 131 temporarily stores a certain amount of data, when datathat is transferred from the host device 201 is written to the NANDmemory 12, or temporarily stores a certain amount of data, when datathat is read from the NAND memory 12 is transferred to the host device201.

The CPU 132 controls the entire semiconductor device 1. For example, theCPU 132 receives a write command, a read command, and an erasure commandfrom the host device 201 and access a corresponding area of the NANDmemory 12, or controls data transfer processing via the buffer 131.

The host interface section 133 is positioned between the connectorsection 21 of the substrate 11 and the CPU 132, and between theconnector section 21 and the buffer 131. The host interface section 133performs interface processing between the controller 13 and the hostdevice 201. For example, a PCIe high-speed signal is transferred betweenthe host interface section 133 and the host device 201.

In addition, the host interface section 133 is arranged at the connectorsection 21 of the substrate 11, that is, so as to be offset towards thefirst edge 13 a of the controller 13. As a result, it is possible toshorten the wires between host interface section 133 and the connectorsection 21 of the substrate 11.

For example, if the host interface section 133 is arranged apart fromthe connector section 21, that is, so as to be offset towards the secondedge 13 b, in the controller 13, a wiring distance is also extended by alength in a longitudinal direction of a controller chip, as may also beseen from FIG. 4. Since the wires are lengthened, a parasiticcapacitance, a parasitic resistance, and a parasitic inductanceincrease, and it is difficult to maintain a characteristic impedance ofsignal wires. In addition, it may cause signal delay.

From the above viewpoint, it would be preferable that the host interfacesection 133 is arranged so as to be offset towards a first edge 13 a ofthe controller 13, and for example, if a command is transferred from ahost device, the connector section 21 receives a signal from the hostdevice 201, and performs signal communication with the host interfacesection 133 via the solder ball 45 a from patterned wires of thesubstrate 11. According to this configuration, operational stability ofthe semiconductor device 1 can be increased.

In addition, it is preferable that an electronic component is notdisposed between the host interface section 133 and the connectorsection 21 of the substrate 11.

As described above, if a wiring distance between the host interfacesection 133 and the connector section 21 is long, impedance of a signalwire may not be stabilized, and a signal may be delayed. Thus, it wouldnot be preferable that an electronic component is disposed between thehost interface section 133 and the connector section 21, in order toform a wire that connects the host interface section 133 to theconnector section 21 in a shortest distance, that is, to form in astraight line.

In addition, an electronic component, such as the power supply circuit17 or the DRAM 14, may cause noise at the time of operation. As theelectronic component is not disposed between the host interface section133 and the connector section 21, that signals transferred between thehost interface section 133 and the connector section 21 are less likelyto contain noise, and thus, the operational stability of thesemiconductor device 1 may be increased.

The memory interface section 134 is positioned between the NAND memory12 and the CPU 132 and between the NAND memory 12 and the buffer 131.The memory interface section 134 performs interface processing betweenthe controller 13 and the NAND memory 12.

In the present embodiment, the memory interface section 134 is arrangedin a side opposite to the connector section 21 of the substrate 11, thatis, arranged so as to be offset towards the second edge 13 b of thecontroller 13. As a result, it is possible to shorten a wiring distancebetween the memory interface section 134 and the NAND memory 12.

A signal from the controller 13 is transferred to the patterned wires ofthe substrate 11 via the solder ball 45 b, and is transferred to thesemiconductor memory 32 from the solder ball 35 a. According to thisconfiguration, a wiring distance is shortened, and operational stabilityof the semiconductor device 1 is increased.

In addition, it is preferable that the power supply circuit 17, the DRAM14, or the like is not disposed also between the memory interfacesection 134 of the controller 13 and the NAND memory 12 on the substrate11. This is for reducing the possibility that signals transferredbetween the memory interface section 134 and the connector section 21contains noise, and for increasing operational stability of thesemiconductor device 1.

FIG. 7 and FIG. 8 are perspective views of the connector sections 21 inthe semiconductor device 1 according to the present embodiment. Asillustrated in FIG. 7, the connector section 21 in the presentembodiment includes, for example, a plurality of first concave curvesections 21 a. In addition, the connector section 21 has a structure inwhich a surface of a conductive layer 20 of the substrate 11 ispartially exposed, and a plurality of first plating sections 21 b isprovided on the surface of the exposed conductive layers 20 in sidesurfaces of the first concave curve sections 21 a, as illustrate in FIG.8. The first plating sections 21 b are plated with, for example, gold,but are not limited to this. In addition, the gold plating is notnecessarily required, and the conductive layer 20 may be in an exposedstate. Furthermore, the conductive layer 20 exposed on the side surfaceof the first concave curve section 21 a may not be a layer shape, and aportion that is electrically connected to the conductive layer 20 may beexposed on the side surface, in a state like a signal line, for example.

In addition, the connector section 21 may have a structure in which anelastic material 310 is included, between the first plating section(first metal section) 21 b and the side surface of the substrate 11, ina state of being electrically connected to the conductive layer 20. Inaddition, for example, rubber, urethane, silicon elastomer, or the likeis used for the elastic material 310.

FIG. 9 illustrates a top sectional view of the connector section 21,when an elastic material is disposed between the first metal section 21b and the substrate 11. In addition, in FIG. 9, the first metal section21 b is provided at a position only in a lateral direction of thesubstrate 11, in the first concave curve section 21 a, but is notlimited to this.

In addition, as described above, the first metal section 21 b isrequired to be electrically connected to the conductive layer 20, but,for example, a signal line may be electrically connected via the centerof the elastic material 310, and the exposed conductive layer 20 and thefirst metal section 21 b may be in contact with each other, in a portionwhich is not covered with the elastic material 310.

In this case, the interface section 221 is pressed by the connectorsection 21 according to the elastic force of the elastic material 310,whereby stability of electric connection is increased.

FIG. 10 is a plan view of the main board 205 mounted on the host device201 to which the semiconductor device 1 is connected. The main board 205includes a substrate 215, and the substrate 215 includes a first surface215 a and a second surface 215 b opposite to the first surface 215 a. Inaddition, the substrate 215 is a multi-layer wiring plate, and includesa conductive layer 225 in the same manner as the substrate 11. In thepresent disclosure, a surface other than the first surface 215 a and thesecond surface 215 b among the surfaces that configures the substrate215 is defined as a “side surface.”

A penetration section 220 that is hollowed out from the first surface215 a to the second surface 215 b of the substrate 215 is provided inthe main board 205, and the main board 205 includes the interfacesection 221 that is electrically connected to the semiconductor device1. A surface that configures the penetration section 220 in thesubstrate 215 is referred to as a “side surface” by the definitiondescribed above.

The penetration section 220 has the same shape as the shape of thesemiconductor device 1, as illustrated in FIG. 10. That is, the mainboard 205 includes a plurality of first convex curve sections 221 a thatrespectively meshes the plurality of first concave curve sections of theconnector section 21 and a plurality of second convex curve sections 222that respectively mesh the plurality of second concave curve sections22, in such a manner that the penetration section 220 has the same shapeas the substrate 11.

The interface section 221 includes the plurality of first convex curvesections 221 a as described above. In addition, the interface section221 has a structure in which a surface of the conductive layer 225 ofthe substrate 215 is partially exposed, and a plurality of secondplating sections 221 b is formed on the surface of the exposedconductive layers 225 in side surfaces of the first convex curvesections 221 a, in the same manner as in a case of the substrate 11. Thesecond plating sections 221 b are also plated with, for example, gold inthe same manner as the first plating sections 21 b, but are not limitedto this. The first concave curve sections 21 a on which plating isperformed are meshed with and in contact with the first convex curvesections 221 a on which plating is performed in the same manner, wherebythe semiconductor device 1 is electrically connected to the host device201. Here, the gold plating may not be necessary, and the conductivelayer 225 may be exposed and in contact with the connector section 21.

In addition, the interface section 221 may have a structure in which anelastic material 310, such as rubber or urethane is included between thesecond plating section (second metal section) 221 b and the side surfaceof the substrate 215, in a state of being electrically connected to theconductive layer 225, in the same manner as in the connector section 21described above.

In this case, the connector section 21 is pressed by the interfacesection 221 according to the elastic force of the elastic material 310,whereby stability of electric connection is increased.

In addition, in the present embodiment, the first two plating sections21 b are provided in one of the first concave curve section 21 a. Here,it is preferable that the first two plating sections 21 b that face eachother conducts the same type of signals, that is, it is preferable thatsignals conducted in one concave curve section are one type. In thiscase, one of the first two plating sections 21 b that face each othermay be in contact with the second plating section 221 b of the firstconvex curve section 221 a that is provided on the substrate 215 of themain board 205. As a result, stability of an electrical connection maybe increased.

In addition, the first plating section 21 b may not be provided on theside surface of the first concave curve section 21 a, and may bearranged in the first concave curve section 21 a in a lateral directionof the substrate 11 as illustrated in FIG. 11, for example. In thiscase, a pressing section 301 is provided on a side opposite to theinterface section 221, in the penetration section 220 of the substrate215, whereby it is possible to increase stability of an electricalconnection between the substrate 11 and the main board 205. In addition,the first plating section 21 b may be provided so as to cover the entirefirst concave curve section. In this case, the first plating sections 21b are provided on three surfaces that form the first concave curvesection 21 a, any one surface of those may be in contact with the secondplating section 221 b of the first convex curve section 221 a. As aresult, stability of an electrical connection can be further increased.In each case, the second plating section 221 b is provided in the firstconvex curve section 221 a, so as to be in contact with the firstplating section 21 b that is provided in the first concave curve section21 a.

Here, an elastic material such as rubber is used for the pressingsection 301. By providing the elastic material in a thickness directionof the substrate 215, the substrate 11 (semiconductor device 1) that isfit into the main board 205 is always in a state of being pressedagainst the interface section 221, and a more stable electrical contactmay be made. The pressing section 301 is not limited to an elasticmaterial formed of rubber and may be a mechanism formed of a spring. Inaddition, the pressing section 301 need not to be necessarily providedon the substrate 215, and may be provided on the second edge 11 d of thesubstrate 11.

In addition, as illustrated in FIG. 4, the substrate 11 includes aplurality of screw holes 11 e. The substrate 11 is also screwed to thesecond fixing sections 231 of the housing 202 in the same manner as inthe main board 205, whereby the semiconductor device 1 may be fixed inthe thickness direction of the substrate 11. Furthermore, the pluralityof the first convex curve sections 221 a and the plurality of the secondconvex curve sections 221 b of the main board 205 are respectivelymeshed with the plurality of the first concave curve sections 21 a andthe plurality of the second concave curve sections 22 of the substrate11, respectively, whereby the semiconductor device 1 is also fixed inthe surface direction of the substrate 11. When the semiconductor device1 is fixed to the second fixing sections 231, it is possible to performmore stable assembly work.

In the present embodiment, the semiconductor device 1 is fixed to thesecond fixing sections 231, in a state in which the main board 205 isfixed to the first fixing sections 230, and at the same time theconnector section 21 and the interface section 221 are electricallyconnected to each other.

In addition, in the present embodiment, fixing of the semiconductordevice 1 and the main board 205 need not to be necessarily performedusing screws, and for example, may be performed by pinning or using amaterial such as an adhesive. The mechanisms or shapes of the firstfixing sections 230 and the second fixing sections 231 may be changed inaccordance with a fixing method.

In each case, height dimension of the protrusions of the first fixingsections 230 and the second fixing sections 231 is uniform, whereby theconnector section 21 and the interface section 221 according to thefixing of the semiconductor device 1 are in contact with each other, andare electrically connected. In addition, in the present embodiment, thefirst concave curve section 21 a and the first convex curve section 221a may not be necessary, and the connector section 21 and the interfacesection 221 may have configurations in which the plurality of the firstplating section 21 b and the plurality of second plating section 221 bare respectively provided on the side surfaces of the substrate 11 andthe side surfaces of the substrate 215.

In addition, in the present embodiment, the second concave curve section22 and the second convex curve section 222 may not be necessary. Whenthe second concave curve section 22 and the second convex curve section222 are provided, it is possible to perform more stable assembly workwhen the above-described semiconductor device 1 is screwed.

Furthermore, in the present embodiment, convex curve sections may beprovided on the substrate 11, and concave curve sections may be providedon the substrate 215. Alternatively, concave curve sections and convexcurve sections may be provided on both of the substrate 11 and thesubstrate 215.

Here, it is assumed that a semiconductor device is not fit into a mainboard, and the semiconductor device is inserted into a slot that isprovided on a surface of the main board. In this case, by inserting thesemiconductor device into the slot that is provided in the main board,the semiconductor device and a host device are electrically connected toeach other. In this case, the semiconductor device and the main boardthat are inserted into the slot are arranged so as to be arrangedsubstantially in parallel. When a semiconductor package is disposed in ahost device, an mounting space having a height of the semiconductorpackage that is disposed in the semiconductor device may be required, asillustrated in, for example, FIG. 5.

In addition, an embedded multimedia card (eMMC) in which a NAND memoryand a controller are incorporated into one package may be disposed in amain board. In this case, the host device may be thinner, but theoperation speed of the eMMC may not be as fast as that of an SSD, andexchange of components may be extremely difficult.

To the contrary, the present embodiment has a structure in which thesemiconductor device 1 is fit into the penetration section 220 of themain board 205. According to this configuration, the main board 205 andthe substrate 11 are provided on substantially the same plane. Thus, thesemiconductor device 1 is located in a space required for mounting themain board 205, in the thickness direction of the host device 201,whereby the host device 201 may be thinner.

Furthermore, in the present embodiment, the semiconductor device 1 andthe main board 205 do not overlap each other. For this reason, it ispossible to suppress heat generated from a component (for example,controller 13) on the semiconductor device 1 from being conducted to themain board 205 through the air.

In addition, the height of the semiconductor package, such as the NANDmemory 12 or the controller 13, which is disposed on the substrate 11,is also substantially the same as that of a plurality of circuitcomponents 216 on the main board 205. As a result, a mounting space neednot to be increased by taking into account an amount of protrusion of acomponent that is disposed on the substrate 11, a space for the mainboard 205 and the semiconductor device 1 can be saved, and the hostdevice 201 may be formed in a thin shape.

Furthermore, the semiconductor device 1 according to the presentembodiment is a device of single-sided mounting. As a protrudingelectronic component is not provided on a rear surface, a mounting spaceof the host device 201 in which the semiconductor device 1 is disposedis decreased, and accordingly the host device 201 may be formed in athin shape.

In addition, as described above, even if an electronic component of thesemiconductor device 1 is disposed on the substrate 215 which directlyconfigures the main board 205, the host device 201 may be formed in athin shape. However, in the present embodiment, the semiconductor device1 can be easily removed. Thus, also from a viewpoint of a performancetest at the time of failure of components, or easiness of chip exchange,the present embodiment would be superior to a case in which thecomponents, such as the NAND memory 12 or the controller 13, aredirectly disposed on the substrate 215.

In addition, the present embodiment does not have a structure in whichthe semiconductor device 1 is inserted into a slot. Thus, a connectionsection that connects the main board 205 to the semiconductor device 1need not be configured along only the first edge 11 a of the substrate11, and for example, may be provided in two edges adjacent to eachother. In this case, it is possible to suppress concentration of wiresin the periphery of the connector section 21, and degree of freedom ofrouting or the like of the wires in the semiconductor device 1 isincreased. For this reason, electronic components, such as the NANDmemory 12, the controller 13, and the DRAM 14 may also be more compactlyarranged, and thus the semiconductor device 1 may also be miniaturized.

Furthermore, in the same manner as in the main board 205, wires throughwhich the semiconductor device 1 and the host device 201 performs datacommunication need not be concentrated to one interface section 221, androuting of wires or component arrangement in the main board 205 can bemore freely designed.

In addition, in the present embodiment, the connector section 21 and theinterface section 221 do not include components to connect each otherand are provided on the side surfaces of the substrate 11 and thesubstrate 215. According to this configuration, not only the number ofcomponents that are used for the host device 201 is reduced, but also aspace for disposing components and wires according to the componentsneed not be considered. As a result, the semiconductor device 1 and themain board 205 are miniaturized, and degree of design freedom isincreased.

Furthermore, in the present embodiment, the semiconductor device 1 isfixed to the housing 202 and at the same time an electrical connectionis established. Thus, it is not necessary to take a space into account,when designing, in order to perform an electrical connection, forexample, to perform insertion and removal, and this also leads to aminiaturization of the host device 201.

The first embodiment is described as above, but the embodiment of thesemiconductor device 1 is not limited to the first embodiment. Next, asemiconductor device according to a second embodiment will be described.The same symbols or reference numerals will be used for elements havingthe same or similar function as that of the first embodiment, anddescription thereof will be omitted. In addition, elements except forthe elements described below are the same as those of the firstembodiment.

Second Embodiment

The semiconductor device 1 according to a second embodiment isillustrated in FIG. 12. In FIG. 12, (a) is a plan view of a top surface,(b) is a plan view of a bottom surface, and (c) is a side view of a sidesurface. In addition, FIG. 13 is a cross-sectional view of thesemiconductor device 1 and the main board 205 according to the secondembodiment.

The connector section 51 according to the present embodiment includes astage 51 a, as illustrated in FIG. 12 and FIG. 13. Since the substrate11 is a multi-layer substrate, the number of layers that configures theconnector section 51 is smaller than that of the other sections. Thatis, since the connector section 51 is processed in a thin shape, thestage 51 a illustrated in FIG. 13 may be formed.

In addition, in the stage 51 a of the substrate 11, a first platingsection (first metal section) 51 b is provided on a surface that issubstantially parallel with the first surface 11 a of the substrate 11,and the first plating section 51 b is electrically connected to theconductive layer 20 of the substrate 11 in the same manner as in thefirst embodiment.

In addition, the main board 205 includes an interface section 251. Theinterface section 251 includes a stage 251 a as illustrated in FIG. 13.In the same manner as in the substrate 11, the substrate 215 thatconfigures the main board 205 is also a multi-layer substrate. Thus, bythinning a portion in the same manner as in the substrate 11 accordingto the present embodiment, the stage 251 a may be formed.

Furthermore, when the semiconductor device 1 is fit into the penetrationsection 220, a second plating section (second metal section) 251 b isprovided on a surface that is in contact with the first plating section51 b, in the stage 251 a. The plating sections are in contact with eachother, whereby the semiconductor device 1 and the host device 201 areelectrically connected to each other.

In the same manner as in the main board 205, the substrate 11 is alsoscrewed to the housing 202, whereby the semiconductor device 1 may befixed in the thickness direction of the substrate 11. Furthermore, thestage 251 a of the main board 205 and the plurality of the second convexcurve sections 221 b are respectively meshed with the stage 51 a of thesubstrate 11 and the plurality of the second concave curve sections 22,whereby the semiconductor device 1 is also fixed in a surface directionof the substrate 11.

In addition, screw holes are provided in the stages 51 b and 251 b andthe substrates 11 and 215 may be screwed to the housing 202. In thiscase, the first plating section 51 b is pressed toward the secondplating section 251 b by the screw, whereby an electrical connection maybe stable. It is preferable that screws used in this case are made of aninsulating material such as plastic.

In addition, the second concave curve section 22 and the second convexcurve section 222 are provided in the substrate 11 and the main board205 in the present embodiment, in the same manner as in the firstembodiment. However, a method of fixing the semiconductor device 1 isnot limited to this, and for example, the semiconductor device 1 mayhave the same structure as that of the stages 51 a and 251 a provided inthe connector section 51 and the interface section 251, respectively.

In addition, also in the present embodiment, an elastic material may bedisposed between the first metal section 51 b and the substrate 11, inthe same manner as in the first embodiment. In the present embodiment, ascrew direction and a pressing direction of the elastic materialsubstantially coincide with each other, whereby an electrical connectionmay be more stable.

The present embodiment also has a configuration in which thesemiconductor device 1 is positioned on substantially the same plane asthe main board 205, a space in which the semiconductor device 1 and themain board 205 are disposed may be reduced, and the host device 201 maybe thinned.

In addition, the present embodiment also describes an example in whichthe semiconductor device 1 is fit into the penetration section 220 ofthe substrate 215, but is not limited to this. In addition, thesemiconductor device 1 is fixed to the second fixing sections 231 alsoin the present embodiment, whereby the semiconductor device 1 and themain board 205 are electrically connected to each other.

Third Embodiment

A sectional side view of the semiconductor device 1 and the main board205 according to a third embodiment is illustrated in FIG. 14. Aconnector section need not to be necessarily provided on the sidesurface of the substrate 11 as described in the first and secondembodiments, and may be disposed on the first surface 11 a of thesubstrate 11 as a connector component. In the same manner, an interfacesection provided in the main board 205 may also be disposed on themounting surface 215 a of the substrate 215.

In the present embodiment, a connector section 61 and an interfacesection 261 are disposed together on the mounting surface 215 a as aconnector component. The connector section 61 and the interface section261 respectively include a metal section 61 a and a metal section 261 aon an upper surface of a component (a surface on a side opposite to themounting surface 215 a). In addition, as illustrated in FIG. 14, theconnector section 61 and the interface section 261 are covered with acover 302.

A sectional view of the connector section 61, the interface section 261,and the cover 302 is illustrated in FIG. 15. As illustrated in FIG. 15,a conductive section 302 a is provided in an inner side of the cover302, and the metal section 61 a provided in the connector section 61 andthe metal section 261 a provided in the interface section 261 areelectrically connected to each other via the conductive section 302 aprovided in the cover 302.

In the present embodiment, the metal section 61 a and the metal section261 a include, for example, multiple pieces and may be respectivelyconnected by a plurality of the conductive sections 302 a that isprovided so as to connect each other. As illustrated in FIG. 16, whenthe connector section 61 and the interface section 261 are covered withthe cover 302, the metal sections 61 a and 261 a of a male terminalshape are inserted into the conductive sections 302 a of a femaleterminal shape, and may be electrically and respectively connected by aconductive layer (not illustrated) provided inside the cover 302.

In addition, plating sections of the connector section 61 and theinterface section 261 according to the present embodiment may beprovided on side surfaces thereof in a state in which the platingsections are in contact with each other. In this case, the semiconductordevice 1 is fixed to the second fixing sections 231, whereby theconnector section 61 and the interface section 261 are in contact witheach other, and are electrically connected to each other. In addition,the connector section 61 and the interface section 261 are fixed to eachother in a state of being pressed by the cover 302, and stability of anelectrical connection is maintained.

In addition, in the present embodiment, the connection section protrudeson each of the mounting surface sides with respect to the substrate 11and the substrate 215, differently from the connector section and theinterface section according to the first and second embodiments.However, as illustrated in FIG. 14, since various electronic componentsincluding the NAND memory 12 are disposed on the substrate 11 and thesubstrate 215, if the connector section 61 and the interface section 261are provided within a range of a height that is formed by protrusion ofthe various electronic components, the breadth of a mounting space neednot be changed, and in the same manner as in the first and secondembodiments, the host device 201 may be formed in a thin shape.

Fourth Embodiment

A connector section 71 of the semiconductor device 1 and an interfacesection 271 of the main board 205, according to a fourth embodiment areillustrated in FIG. 17.

As illustrated in FIG. 17, a connector section 71 that is provided inthe semiconductor device 1 includes a plurality of male terminals 71 a.In addition, an interface section 271 that is provided on the mountingsurface 215 a of the substrate 215 includes a plurality of femaleterminals 271 a that includes the same number of pieces as the maleterminals 71 a, and an electrical connection is established by the maleterminals 71 a being inserted into the female terminals 271 a.

Since an electrical connection according to the present embodiment ismade by inserting terminals of a pin shape into each other, thesemiconductor device 1 according to the present embodiment has a moreelectrically stable structure than a structure in which conductivematerials (for example, plating materials) are merely in contact witheach other.

Furthermore, the connector section 71 and the interface section 271 inthe present embodiment respectively have structures in which themounting surface sides of the substrate 11 and the substrate 215protrude, but as illustrated above, various electronic componentsincluding the NAND memory 12 are disposed on the substrate 11 and thesubstrate 215. Thus, if the connector section 71 and the interfacesection 271 are provided within a range of a height that is formed byprotrusion of the various electronic components, the breadth of anmounting space need not be changed, and as a result, the host device 201may be formed in a thin shape.

Fifth Embodiment

FIG. 18 illustrates a semiconductor device 1 according to a fifthembodiment, which is disposed in a tablet type portable computer 201. Inthe fifth embodiment, the mounting surface 11 a of the substrate 11 ispositioned on a side opposite to the mounting surface 215 a of thesubstrate 215 of the main board 205. Thus, in the semiconductor device 1according to the present embodiment, a protruded component faces a sideopposite to a display module.

In the configuration described above, the semiconductor device 1 may beless subjected to the heat generated in the display module, and theoperation stability of the semiconductor device 1 may be increased. Inaddition, since the controller 13 and the housing 202 of the tablet typeportable computer 201 are separated from each other, the heat emittedfrom the controller 13 is suppressed from being diffused to a surface ofthe tablet type portable computer 201, and it is possible to preventsurface temperature of the tablet type portable computer 201 fromincreasing. For this reason, a user can safely use the tablet typeportable computer 201, and it is possible to improve user convenience.

In addition, the substrate 11 and the substrate 215 are positioned onsubstantially the same plane, also in the present embodiment. Thus, thesemiconductor device 1 is accommodated in a space required for mountingthe main board 205, in the thickness direction of the tablet typeportable computer 201, whereby the tablet type portable computer 201 maybe formed in a thin shape.

In addition, a connection section that connects a connector section toan interface section in the present embodiment may have one of theconfigurations described in the first to fifth embodiments.

Sixth Embodiment

The main board 205 according to a sixth embodiment is illustrated inFIG. 19. As illustrated in FIG. 19, a notch section 290 is provided in asubstrate 216 of a substantially rectangular shape in the presentembodiment. The semiconductor device 1 is disposed in a position of thenotch section 290 as illustrated in FIG. 20.

In addition, a connection section that connects a connector section toan interface section in the present embodiment may have one of theconfigurations described in the first to fifth embodiments. Theconnector section 21 and the interface section 221 that are described inthe first embodiment are illustrated in FIG. 19 and FIG. 20.

Since the substrate 11 and the substrate 215 are in parallel onsubstantially the same plane, the semiconductor device 1 is mounted in aspace required for disposing the main board 205, in the thicknessdirection of the host device 201, whereby the host device 201 may beformed in a thin shape.

In addition, the notch section 290 is provided in the presentembodiment, but this configuration may not be necessary. The substrate11 and the substrate 215 on which components are disposed may berespectively fixed in parallel only to the first fixing section 230 andthe second fixing section 231. Also in this case, height dimension ofthe protrusion sections of the first fixing sections 230 and the secondfixing sections 231 is uniform, whereby the host device 201 may beformed in a thin shape. According to the fixing of the semiconductordevice 1, the semiconductor device 1 and the main board 205 areelectrically connected to each other.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. An electronic apparatus, comprising: a housing; afirst circuit board including a first engaging portion configured to fixthe first circuit board to the housing, and a first terminal; and asecond circuit board including a second engaging portion configured tofix the second circuit board to the housing, and a second terminalelectrically connected to the first terminal.
 2. The electronicapparatus according to claim 1, wherein the first terminal is formed ona side surface of the first circuit board, the second terminal is formedon a side surface of the second circuit board, and the first and secondterminals are coupled to each other.
 3. The electronic apparatusaccording to claim 2, wherein the first terminal is located at aprotrusive portion formed on the side surface of the first circuitboard, and the second terminal is located at a recessed portion formedon the side surface of the second circuit board.
 4. The electronicapparatus according to claim 3, wherein the first and second terminalsare coupled to each when the protrusive portion is fit in the recessedportion.
 5. The electronic apparatus according to claim 2, wherein atleast one of the first and second terminals includes an elastic layerthat is deformed when the first terminal is coupled to the secondterminal.
 6. The electronic apparatus according to claim 1, wherein thefirst circuit board includes an interface unit configured to transmit aread signal and a write signal to the second circuit board, and thesecond circuit board includes a semiconductor memory unit and a controlunit configured to control the semiconductor memory unit to read andwrite data in accordance with the read signal and the write signal,respectively.
 7. The electronic apparatus according to claim 1, whereinone of the first and second terminals is formed at a portion of thecorresponding circuit board recessed from an upper surface thereof, andthe other one of the first and second terminals is formed at a portionof the corresponding board recessed from a lower surface thereof.
 8. Theelectronic apparatus according to claim 1, wherein one of the first andsecond terminals is formed in a hole extending from an upper surface ofthe corresponding circuit board, and the other one of the first andsecond terminal is a protrusion formed on the corresponding circuitboard and fit in the hole.
 9. The electronic apparatus according toclaim 1, wherein the first terminal is formed on an upper surface of thefirst circuit board, the second terminal is formed on an upper surfaceof the second circuit board, and the first and second terminals areelectrically connected with a connecting member covering the first andsecond terminals.
 10. The electronic apparatus according to claim 9,wherein the first terminal includes a plurality of protrusions formed onthe upper surface of the first circuit board, the second terminalincludes a plurality of protrusions formed on the upper surface of thesecond circuit board, and the connecting member includes a plurality ofrecessed portions engaged with the protrusions of the first and secondterminals.
 11. The electronic apparatus according to claim 1, whereinthe first circuit board includes an opening, and the second circuitboard is fit in the opening.
 12. The electronic apparatus according toclaim 1, wherein the first circuit board includes a notched portion onan edge thereof, and the second circuit board is fit in the notchedportion.
 13. An electronic apparatus, comprising: a first circuit boardincluding an interface unit disposed thereon and configured to transmita read signal and a write signal, and a first terminal; and a secondcircuit board including a semiconductor memory unit and a control unitconfigured to control the semiconductor memory unit to read and writedata, which are disposed on a surface thereof, and a second terminalcoupled to and electrically connected with the first terminal.
 14. Theelectronic apparatus according to claim 13, wherein the first terminalis formed on a side surface of the first circuit board, and the secondterminal is formed on a side surface of the second circuit board. 15.The electronic apparatus according to claim 14, wherein the firstterminal is located at a protrusive portion formed on the side surfaceof the first circuit board, and the second terminal is located at arecessed portion formed on the side surface of the second circuit board.16. The electronic apparatus according to claim 15, wherein the firstand second terminals are coupled when the protrusive portion is fit inthe recessed portion.
 17. The electronic apparatus according to claim13, wherein at least one of the first and second terminals includes anelastic layer that is deformed when the first terminal is coupled to thesecond terminal.
 18. The electronic apparatus according to claim 13,wherein the first circuit board includes an opening, and the secondcircuit board is fit in the opening.
 19. The electronic apparatusaccording to claim 13, wherein the first circuit board includes anotched portion on an edge thereof, and the second circuit board is fitin the notched portion.
 20. The electronic apparatus according to claim13, wherein the first circuit board is a part of a host device.